The present invention relates to a semiconductor package, and more particularly, to a multi-chip package in which electrical and mechanical connections are formed between a substrate and a semiconductor chip and between semiconductor chips using bumps and metal patterns.
As is well known in the art, packaging technology has been developed to be capable of mounting an increased number of packages to a substrate having a limited size, that is, to decrease the size of packages. For instance, various types of chip size packages (hereinafter, referred to as “CSPs”), in which the size of semiconductor chips is greater than 80% of the overall size of packages, have been developed in the art. While not shown in a drawing, in these CSPs, because an increased number of packages can be mounted to a substrate having a limited size when compared to typical semiconductor packages. CSP advantages are provided in that it is possible to realize a product having a small size and high capacity.
However, while the CSPs provide advantages in that the number of packages to be mounted can be increased through the decrease in the size thereof, because one semiconductor chip is placed in one package, as is common in typical semiconductor packages, limitations necessarily exist in matching impedance to increase capacity and ensure high speed operation, and therefore, it is difficult to realize a system having high capacity.
Under these situations, in an effort to decrease the size of a package and increase the capacity of the package, research has actively been made to develop a stack package and a multi-chip package in which two or three semiconductor chips are placed in one package.
The multi-chip package is manufactured by placing at least two semiconductor chips having different functions or at least two semiconductor chips having the same function in one package. Generally, the multi-chip package is manufactured by packaging two to four semiconductor chips in the state in which they are simply arranged on a substrate or by packaging at least two semiconductor chips having different functions and sizes in the state in which they are vertically stacked.
Hereafter, a conventional multi-chip package will be briefly described with reference to FIG. 1.
Referring to FIG. 1, in a conventional multi-chip package 10, two semiconductor chips 12 and 14 are shown having different functions and sizes which are stacked in a face-up type on a substrate 11 which has electrode terminals 11a, by way of adhesives 13 and 15. Bonding pads 12a and 14a of the respective semiconductor chips 12 and 14 and the electrode terminals 11a of the substrate 11 are electrically connected by metal wires 16. The upper surface of the substrate 11, including the stacked semiconductor chips 12 and 14 and the metal wires 16, is molded by an encapsulant 17 such as an EMC (epoxy molding compound). Solder balls 18, as mounting units to external circuits, are attached to ball lands 11b that are placed on the lower surface of the substrate 11.
However, in the conventional multi-chip package as described above, when considering that the bonding pads of the respective semiconductor chips and the electrode terminals of the substrate are electrically connected with each other by the metal wires, a top cavity should be increased so as to prevent wire loops from being damaged. Due to this fact, a problem may arise in that the overall thickness of the package increases.
Also, in the case of placing center pad type semiconductor chips, since the metal wires serving as electrical connection units between the bonding pads and the electrode terminals form thin and long loops, protective coatings should be applied to the metal wires. Due to this fact, problems may arise in that the manufacturing cost and the number of processes increase, thermal characteristics deteriorate, and an operating speed decreases due to limitations in impedance matching.
In addition, in the conventional multi-chip package, due to the fact that electrical connections between the bonding pads of the respective stacked semiconductor chips and the electrode terminals of the substrate are formed by the metal wires, the metal wires connected with the lower semiconductor chip and the metal wires connected with the upper semiconductor chip are likely to be brought into contact with each other in a wire bonding process, as well as, in a subsequent molding process using the EMC. Thereby defects, such as short circuits, in the conventional multi-chip package can occur.
Further, because the conventional multi-chip package has a structure in which the semiconductor chips are stacked in the form of a step, limitations necessarily arise in selecting semiconductor chips to be stacked, as in the case that an upwardly positioned semiconductor chip should have a size capable of completely exposing the bonding pads of a downwardly positioned semiconductor chip.